1. Field of the Invention
The present invention relates to a thin-film transistor and a fabrication method thereof and more particularly, to a thin-film transistor that is capable of a highly reliable operation for use as a liquid crystal display (LCD) device and others and that is readily fabricated, and a fabrication method of the transistor.
2. Description of the Prior Art
Unlike conventional monolithic transistors that are formed in the inside of a semiconductor substrate, thin-film transistors are fabricated by stacking several thin films on a substrate. Therefore, the thin-film transistors have a simple and easy-to-fabricate configuration compared with the monolithic transistors. As a result, the thin-film transistors have been in widespread use as, for example, switching elements in a large-sized electronic device such as an LCD device.
Further, the simplicity of the device configuration and fabrication method of the thin-film transistors makes it possible to fabricate various applied products at low cost, which contributes to popularization of them on the market.
In recent years, the above simplicity of the thin-film transistors has been further improved and progressed.
Specifically, the basic components of a thin-film transistor are a substrate, a semiconductor thin film in which a conductive channel is formed on operation, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The source and drain electrodes, which are located apart from each other on a same side of the semiconductor film, are electrically connected to the semiconductor film. The gate insulating film is located on an opposite side of the semiconductor film to the source and drain electrodes. The gate electrode, which is located on the same side of the semiconductor film as the gate insulating film, is opposite to the semiconductor film through the gate insulating film. The conductive channel is formed in the gate-side surface region of the semiconductor film under application of a proper gate voltage.
The semiconductor thin film is typically formed by an undoped (or, i-type) semiconductor material. In this case, there is the need for interposing an n.sup.+ -type semiconductor film between the i-type semiconductor film and the opposing source and drain electrodes. The n.sup.+ -type semiconductor film is used to form source and drain contact regions between the undoped semiconductor film and the source and drain electrodes, respectively. The source and drain contact regions provide good Ohmic contacts therebetween.
From this point of view, various contrivances have been continued to minimize the number of necessary films and the number of necessary fabrication processes.
When the n.sup.+ -type semiconductor film serving as the source and drain contact regions is provided, the source and drain electrodes are short-circuited to each other by the n.sup.+ -type semiconductor film. Therefore, it is necessary to add a process of selectively removing the n.sup.+ -type semiconductor film by etching in a back channel section between the source and drain electrodes.
However, if the n.sup.+ -type semiconductor film is formed to be extremely thin, the etching process for selectively removing the back channel section of the n.sup.+ -type semiconductor film can be omitted without arising any problem about the off-resistance of the thin-film transistor. This knowledge was disclosed in the Japanese Non-Examined Patent Publication No. 59-172774 published in 1984.
FIG. 1 shows a first conventional thin-film transistor of the inverted staggered (or, bottom gate) type, which is disclosed in the Japanese Non-Examined Patent Publication No. 59-172774.
In FIG. 1, a gate electrode 1102 is formed on an insulating substrate 1101. A gate insulating film 1103 is formed on the substrate 1102 to cover the gate electrode 1102. An undoped or i-type amorphous silicon film 1104 is formed on the gate insulating film 1103. An n.sup.+ -type amorphous silicon film 1105 for source and drain contact regions is formed on the i-type amorphous silicon film 1104. A drain electrode 1106 and a source electrode 1107 are formed on the n.sup.+ -type amorphous silicon film 1105 to be apart from each other.
FIG. 2 shows a second conventional thin-film transistor of the staggered (or, top gate) type, which is disclosed in the Japanese Non-Examined Patent Publication No. 59-172774.
In FIG. 2, a drain electrode 1106 and a source electrode 1107 are formed on an insulating substrate 1101 to be apart from each other. An n.sup.+ -type amorphous silicon film 1105 for source and drain contact regions is formed on the substrate 1101 to cover the drain and source electrodes 1106 and 1107. The n.sup.+ -type amorphous silicon film 1105 is contacted with the substrate 1101 in a back channel section 1204 between the drain and source electrodes 1106 and 1107. An undoped amorphous silicon film 1104 is formed on the n.sup.+ -type amorphous silicon film 1105. A gate insulating film 1103 is formed on the undoped amorphous silicon film 1104. A gate electrode 1102 is formed on the gate insulating film 1103.
In FIGS. 1 and 2, the n.sup.+ -type amorphous silicon film 1105 is extremely thin to give a high off-resistance of 10.sup.9 .OMEGA. or higher between the source and drain electrodes 1107 and 1106. The n.sup.+ -type amorphous silicon film 1105 is not removed in the back channel section 1204. In other words, the n.sup.+ -type amorphous silicon film 1105 is continuous from the drain electrode 1106 to the source electrode 1107.
A third conventional thin-film transistor was disclosed in the Japanese Examined Patent Publication No. 6-22244 published in 1994 (which corresponds to the Non-Examined Patent Publication No. 62-81064 published in 1987). This transistor has phosphorus-doped regions in the respective surface regions of transparent source and drain electrodes and a transparent glass substrate. The phosphorus-doped regions are formed by exposing the source and drain electrodes and the substrate to phosphine (PH.sub.3) plasma. The phosphorus-doped regions have substantially the same action as that of the extremely-thin n.sup.+ -type amorphous silicon film 1105 in FIGS. 1 and 2. Therefore, an etching process in the back channel section can be omitted while ensuring an Ohmic contact.
In detail, as shown in FIG. 3, a drain electrode 1106 and a source electrode 1107, which are formed by patterning a transparent conductive film, are located on a transparent glass substrate 1141 to be apart from each other. The drain and source electrodes 1106 and 1107 include phosphorus-doped regions 1106A and 1107A in their tops, respectively. The substrate 1141 includes a phosphorus-doped region 1141A in an exposed area between the drain and source electrodes 1106 and 1107. The phosphorus-doped regions 1106A, 1107A, and 1141A are formed by a plasma doping process of phosphorus.
A patterned undoped amorphous silicon film 1104 is formed on the substrate 1141 to partially cover the drain and source electrodes 1106 and 1107. A patterned gate insulating film 1103 is formed on the undoped amorphous silicon film 1104. A gate electrode 1102 is formed on the gate insulating film 1103. A silicon nitride film 1108 is formed on the substrate 1141 to cover the drain and source electrodes 1106 and 1107, the amorphous silicon film 1104, the gate insulating film 1103, and the gate electrode 1102.
A phosphorus-doped region 1145 is formed in the amorphous silicon film 1104 in its bottom. The phosphorus-doped region 1145 extends along the interfaces of the amorphous silicon film 1104 with the opposing drain and source regions 1106 and 1107 and with the opposing substrate 1141. The parts of the phosphorus-doped region 1145 located on the drain and source electrodes 1106 and 1107 serve as the Ohmic contact regions. The phosphorus-doped region 1145 is formed by diffusion or doping of the phosphorus atoms contained in the phosphorus-doped regions 1106A, 1107A, and 1141A.
FIG. 4 shows a fourth conventional thin-film transistor, which was disclosed in the IEEE ELECTRON DEVICE LETTERS, Vol. 9, No. 2, 1988, pp. 90 to 93. In this case, an additional insulating film is formed on a semiconductor thin-film on an opposite side to a gate electrode. The additional insulating film is selectively etched to be left only in a back channel section. Phosphorus ions are selectively implanted into the semiconductor thin-film using the remaining additional insulating film as a mask at a low acceleration energy. Thus, Ohmic contact regions for source and drain electrodes are made.
In detail, as shown in FIG. 4, a gate electrode 1102 is formed on a glass substrate 1241. A gate insulating film 1103 is formed on the substrate 1241 to cover the gate electrode 1102. An undoped amorphous silicon film 1104 is formed on the gate insulating film 1103. A patterned silicon nitride film 1209 is formed on the undoped amorphous silicon film 1104 to be opposite to the gate electrode 1102. A drain electrode 1106 and a source electrode 1107 are formed on the undoped amorphous silicon film 1104 and the gate insulating film 1103 to be apart from each other. The drain and source electrodes 1106 and 1107 are contacted with not only the undoped amorphous silicon film 1104 but also the silicon nitride film 1209.
After forming the silicon nitride film 1209, this film 1209 is selectively etched in such a way that the remaining part of the film 1209 has a width substantially equal to the channel length L. Then, using the remaining silicon nitride film 1209 as a mask, phosphorus ions are selectively implanted or doped at a low acceleration energy of 5.5 kV while exposing the entire exposed surfaces including those of the exposed amorphous silicon film 1104 and the silicon nitride film 1209 to a phosphine (PH.sub.3) gas. Thus, two phosphorus-doped regions 1245 are formed in the undoped amorphous silicon film 1104 at its each end, and at the same time, a phosphorus-doped region 1209A is formed in the silicon nitride film 1209 in its top. No phosphorus ions are implanted into the part of the film 1104 just beneath the film 1209.
Thereafter, the ion-implanted amorphous silicon film 1104 is selectively etched to be a specific transistor island, as shown in FIG. 4. Then, the drain and source electrodes 1106 and 1107 are formed. The phosphorus-doped regions 1245A in the silicon film 1104 serve as Ohmic contact regions for the drain and source electrodes 1106 and 1107.
A fifth conventional thin-film transistor is shown in FIG. 5, which was disclosed in the Japanese Non-Examined Patent Publication No. 7-263702 published in 1995. In this transistor, ion implantation and plasma doping processes are successively carried out using a channel protection film as a mask. The later plasma doping process has a function of repairing the defects caused by the former ion implantation process. Subsequently, a chromium (Cr) film used for source and drain electrodes is formed on an undoped amorphous silicon film so as to generate reliable Ohmic contact regions made of a chromium silicide.
In detail, as shown in FIG. 5, a gate electrode 1102 is formed on a transparent glass substrate 1141. A gate insulating film 1103 is formed on the substrate 1141 to cover the gate electrode 1102. A patterned, undoped amorphous silicon film 1104 is formed on the gate insulating film 1103. A patterned silicon nitride film 1219 is formed on the undoped amorphous silicon film 1104 to be opposite to the gate electrode 1102. A drain electrode 1106 and a source electrode 1107 are formed on the gate insulating film 1103 to be apart from each other. The drain and source electrodes 1106 and 1107 are contacted with the undoped amorphous silicon film 1104 at each side.
After forming the silicon nitride film 1219, this film 1219 is selectively etched in such a way that the remaining part of the film 1219 has a width substantially equal to the channel length L. Then, using the remaining silicon nitride film 1219 as a mask, phosphorus ions are implanted at an acceleration energy of 30 kV or lower. This implantation process is termed the "ion-shower process". Thus, phosphorus-doped regions 1245A are formed in the undoped amorphous silicon film 1104 at its each end. No phosphorus ions are implanted into the part of the film 1104 just beneath the film 1219.
Subsequently, a plasma doping process is performed in a plasma-CVD chamber using a hydride or fluoride of a three- or five-valence element (such as phosphine) to repair the defects in the amorphous silicon film 104.
Further, without breaking the vacuum in the plasma-CVD chamber, a chromium film is deposited to produce a chromium silicide at the interface between the chromium film and the phosphorus-doped regions 1245A. Thereafter, the chromium film is patterned to form the drain and source electrodes 1107 and 1106. The chromium silicide film is left under the remaining chromium film and therefore, good Ohmic contact are generated between the drain and source electrodes 1106 and 1107 and the corresponding phosphorus-doped regions 1245A of the amorphous silicon film 1104. This ensures a good pattern-alignment margin.
With the first to fifth conventional thin-film transistors described above, the improvement is performed for the purpose of omitting some patterning or film-formation process or processes in a fabrication process sequence of a thin-film transistor. However, there is a drawback that they cannot provide a good operational characteristic and reliability with a good fabrication yield, while they offer an advantage of increased simplicity.
Specifically, a first problem is that the off-characteristic of a thin-film transistor degrades and accordingly, the operational reliability is decreased with age or time. This is because each of the first to fifth conventional transistors has the following disadvantages in device configuration and fabrication method.
With the first and second conventional transistors shown in FIGS. 1 and 2, which were disclosed in the Japanese Non-Examined Patent Publication No. 59-172774, the n.sup.+ -type amorphous silicon film 1105 with good electrical conductivity exists in the back channel section 1204, although the conductive film 1105 is extremely thin. Accordingly, a leakage current flowing between the drain and source electrodes 1106 and 1107 cannot be minimized.
With the third conventional transistor shown in FIG. 3, which was disclosed in the Japanese Examined Patent Publication No. 6-22244, the phosphorus-doped region 1145 of the amorphous silicon film 1104 extends along the back channel section 1204. This phosphorus-doped region 1145 results in a leakage current between the drain and source electrodes 1106 and 1107.
Therefore, the first to third conventional transistors usually have the transfer characteristic as shown by the curve "b" in FIG. 8, which is poor in off-characteristic.
A second problem is that the n.sup.+ -type amorphous silicon film 1105 having a high off-resistance of 10.sup.9 .OMEGA. or higher is very difficult to be realized in the first and second conventional transistors in FIGS. 1 and 2. This is because the electric resistance of the film 1105 is very sensitive to the doping concentration of phosphorus from the phosphine gas and others and consequently, the formation process of the film 1105 is difficult to be controlled. If the electric resistance is high, the Ohmic contact with the source and drain electrodes 1107 and 1106 will deteriorate, while the leakage current between the electrodes 1107 and 1106 is decreased.
With the third conventional transistor shown in FIG. 3, the plasma doping process is difficult to be controlled. If this plasma doping process is continued for several minutes, the off-resistance will decrease due to the leakage current. Therefore, the doping time during the plasma doping process must be set as short as one minute. This means that no good reproducibility is realized.
Therefore, an extremely poor off-characteristic as shown with the curve "a" in FIG. 8 has been often exhibited.
A third problem is that a leakage current tends to flow between the drain and source regions 1106 and 1107 through the phosphorus-doped region 1209A formed in the top of the upper insulating film 1209 in the fourth conventional transistor shown in FIG. 4. Since no phosphorus ions are implanted into the undoped amorphous silicon film 1104 in the back channel section 1204, no leakage current flows through the region 1204.
Further, because the drain and source electrodes 1106 and 1107 are separated by an opening at a location on the insulating film 1209, the distance between the opposing ends of the electrodes 1106 and 1107 is shorter than the channel length. This means that the fabrication yield is lowered.
A fourth problem is that a process of forming the channel protection film 1209 or 1219 is necessary and as a result, the number of fabrication processes is increased in the fourth and fifth conventional transistors shown in FIGS. 4 and 5.
Because a chromium film is used for the source and drain electrodes 1107 and 1106 to form a chromium silicide in the fifth conventional transistor in FIG. 5, the lateral distance between the source and drain electrodes 107 and 106 can be made longer compared with the fourth conventional transistor in FIG. 4. However, the surface of the channel protection film 1219 is ion-implanted as in the fourth conventional transistor. Thus, the leakage current cannot be thoroughly prevented in the fifth conventional transistor.
The obtainable transfer characteristic of the fifth conventional transistor in FIG. 5 is shown with the curve "c" in FIG. 8, which has a considerable improvement, as compared to the curves "b" and "a", but insufficient.
A fifth problem is that the fifth conventional transistor in FIG. 5, which has the improved characteristic as shown with the curve "c" in FIG. 8, increases the number of steps in the fabrication processes. Specifically, the fifth conventional transistor necessitates a hydrogen plasma annealing process in conjunction with the plasma doping process, in addition to the ion implantation process. This is because the transistor is damaged by the ion implantation and thus, any repairing process is required for repairing the damage.